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Recent content by keerthna

  1. K

    If modulation index is a floating point number, how do I represent in FPGA?

    If modulation index is a floating point number, how do i represent in fpga? I am designing a pwm module and i want to have a 4-bit input which is the modulation index and based on which the output of the sine wave changes. For example module lut(clk,mi,sineout); input clk; output sineout...
  2. K

    How to generate a triangular wave with some particular frequency in verilog?

    I want to generate a triangle wave of say 100khhz frequency. Can anyone help me in how to do it? In general i can use a counter which increments and decrements and generate a triangle wave. But what to do if i want a frequency?
  3. K

    How to create a sine wave using lut in verilog?

    So if i have to generate a 50hz sine wave and my system clock frequency is 33Mhz and i take n=16, then according to fout=(M*fc)/2^n i get M=0.0992 so the lut will have values starting from sin(0.099) , sin(0.198) this way? till sin (90) ??
  4. K

    How to create a sine wave using lut in verilog?

    Using excel I can generate the table of values. But my problem is how many values should i store and what should be the difference between those values? I mean sin(0) , sin(10) like this how many and what values should i store ideally?
  5. K

    How to create a sine wave using lut in verilog?

    I DID GOOGLE BUT COULDNT GET A CLEAR PICTURE OF IT. HOW DO I STORE THE VALUES? what values are stored in the lut?
  6. K

    How to create a sine wave using lut in verilog?

    I want to use the lut approach to create a sine wave. but i dont know what exactly to have in that lut. can anyone please explain in detail. thanks in advance
  7. K

    Can we use the sine wave generated by IP cores for PWM generation in Verilog?

    I MEANT THAT THE TEST BENCH CAN ONLY BE SIMULATED. HOW CAN I SYNTHESIZE IT? i mean i want to synthesize the code using spartan6 fpga. so if i write a test bench, how can i synthesize?
  8. K

    [SOLVED] How does Xilinx IP cores for sine waves generate Sine wave?

    But if i want to change the modulation index in accordance with the carrier, is it possible to do the same with ipcores? if not then how do i generate sine waves with variable modulation index?
  9. K

    Can we use the sine wave generated by IP cores for PWM generation in Verilog?

    I have one verilog module which generates the sine wave using the ip cores from xilinx. I now create another verilog module which generates a triangle wave and uses the sine wave generated previously for the pwm generation. Is this possible without creating a test bench? Also can the modulation...
  10. K

    Can we use the sine wave generated by IP cores for PWM generation in Verilog?

    I want to use PWM using sine triangle generation. If I generate sine waves using Ip cores can that sine wave be instantiated in another module which generates the triangle waves? I mean without writing a test bench can we connect these signals in Verilog?
  11. K

    [SOLVED] How does Xilinx IP cores for sine waves generate Sine wave?

    Sine wave is analog in nature. And FPGA can read only digital values. So how will IP cores generate sine waves? I didnt get the actual meaning here. Can anyone please explain
  12. K

    How to increment a value in verilog?

    I am incrementing up and down variables. High becomes '1' when a particular value of count is reached like if(count1==23'b______) begin count1=0; high=1; end - - - Updated - - - I am incrementing up and down variables. High becomes '1' when a particular value of count is reached like...
  13. K

    How to increment a value in verilog?

    I wrote a piece of code for the incrementation of a variable at certain conditions but it is not happening the way it has to be. Can anyone please help me out with the same. Here is my sample code reg[31:0]nomfreq,nc1; reg [2:0] up,down; reg high; initial begin up=0 down=0; high=0 end...
  14. K

    How to read the values of memory into a register in verilog?

    Yes I made the necessary changes to the code and it is working fine. Thanks a lot for all your help :)
  15. K

    How to read the values of memory into a register in verilog?

    i added that for loop and also initialised them. can you please suggest a solution for my problem? how to read those count values and average them?
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