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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY mult4 IS
PORT (
a, b : IN std_logic_vector(3 DOWNTO 0);
cout : OUT std_logic_vector(7 DOWNTO 0)
);
END mult4;
ARCHITECTURE behave OF mult4 IS
SIGNAL result : std_logic_vector(7 DOWNTO 0)...
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