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Recent content by kapil86

  1. K

    Why Gilbert noise figure is more at IF frequency than at RF frequency?

    Re: Gilbert Noise figure sir, i am talking about active mixer not passive and i want to know the region, why noise figure is more at IF frequency than RF frequency. Thank you
  2. K

    Why Gilbert noise figure is more at IF frequency than at RF frequency?

    Respected sir/mam I have designed Gilbert mixer, When i do noise figure(NF) simulation at IF (2 MHz) and RF (2.4 GHz) Frequencies, i found that NF at IF is more than (4dB) to RF frequency. What is the region for that. someone help me please. Thank you
  3. K

    [SOLVED] how to convert 2 dimensional array vector into 1 dimensional array vector in verilog?

    I have designed my code in system verilog (Modelsim) and instantiated 2 dimensional array vector, there it shows no problem in compilation and simulation but for synthesizing (Xilinx) the code it shows error(illegal reference to net array) for 2 d array vector... so I would like to convert this...
  4. K

    Extracted parasitic of cadence inductor using HFSS

    I am trying to extract cadence inductor (UMC library) parasitics in HFSS by importing gds file. After importing gds file, inductor layout is visible in HFSS window with so many layers. Issue is that cadence generated 2D file and HFSS want 3D file to simulate. I converted inductor 2D layout into...
  5. K

    Use of ASITIC inductor Lauout in LNA circuit simulation and layout in Cadence

    ok thanks Mr. fanshuo
  6. K

    Use of ASITIC inductor Lauout in LNA circuit simulation and layout in Cadence

    Dear fanshuo, Thank you to reply, the Schematic simulation i will do using ideal R,L,C. but how to verify my Schematic simulation results to post layout simulation its also necessary at high frequencies.
  7. K

    Use of ASITIC inductor Lauout in LNA circuit simulation and layout in Cadence

    I have extracted PI model parasitics of inductor in ASITIC and imported CIF file in Cadence. It is visible in cadence layout window. How to use this layout of inductor in my LNA (low noise amplifier) circuit and layout for Schematic and DRC ,LVS respectively. Please help me its very urgent for...
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