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Hi,
I agree and I am working on it, but getting hard time to resolve.
Will surely display the code if I come up with any solution to it, in the meanwhile suggestion and solutions are most welcome.
Hi,
The module of stage 1 and stage 2 are in a flow of the process, when stage 1 is completed then stage 2 starts.
I need a solution, in which I can reset the counter value at stage 1 and reset the counter to count from zero at stage 2.
Since, I have provided the condition in which...
Hello, The following code is compiled and is working in parallel, Please help me to make these code work sequentially, i.e after stage1 counter should reset itself and starts from 0 for the stage2. The following codes has Module1- stage1 and module2-stage2.
module stage1(...
Re: implementation of output wrt clock in verilog
Hi dpaul, for this module I have 1 bit I/O, I want make output work according to the count. I am confused with what logic I should use in order to make it work.
Thank you
Thank you for the advice, this code is not working. I am confused may I am short of knowledge about the Verilog. But I am working on it.
If anyone can help with the suggestion to improve, its always welcome.
I want to design module in which outputs are sequential and are displayed with the interval of count of the counter. for example: if count is from 1 to 5, we are getting y0, y1,y2,y7 & y10 as output in the flow, and when count is from 2 to 9 we get y15 as output and y0, y1,y2,y7 & y10 = low or...
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