Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: clocks....
In electronics and especially synchronous digital circuits, a clock signal is a signal used to coordinate the actions of two or more circuits. Think about synchronous. But this is very wide definition. Usually clock is the fastest signal in your circuit and operations of your...
I am developing an application which needs to work between RTL and GATE.
i.e. it uses some information from RTL level and some information from corresponding GATE design. It is obvious that during synthesis, tools (DC, RTLC) do changes the names as well as hierarchy. I am facing problem while...
generating saif file
saif file - contains toggle counts and time information like how much time a signal was in 1 state(T1), 0 state(T0) , x state (TX). Also in backward saif file you can have timing information, arc information just like .lib (read saif manual).
vcd file - contains value...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
