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Recent content by kalpana.aravind

  1. K

    need help - convolution using DFT

    linear convolution using dft Hi, i want to know, how to do the linear convolution of two sequences, x1(sinusoid of frequency f1) and x2(sinusoid of frequency f2) using DFT in MATLAB. please provide any website address where to find the MATLAB code for DFT. any suggestions welcome. thanks
  2. K

    Need help - embedded linux

    Hi everyone, I want to know about embedded linux . please send the useful article, paper links, websites, online books on embedded linux, more about its kernel architecture, i would like to know how it dffers from the general linux, how the bootup time is reduced in embedded linux, methods to...
  3. K

    Help needed -MIPS pipeline design

    Hi All, Please forward me the useful links for MIPS pipeline design in verilog. Any reference pipeline design examples. I would like to know about pipeline design for 16 bit R2000 MIPS procesoor. Any suggestions welcome Thanks & Regards,
  4. K

    Pipilene Design for MIPS processor

    mips processor design Hi All, Please send me the links of reference designs of MIPS pipeline in verilog. I would like to know about pipeline design for 16bit MIPS R2000 processor. Any suggestions welcome. Thanks and Regards,
  5. K

    Help needed - Writing testbench in verilog

    Hi All, following is the verilog code for uart.v How to write a self checking test bench that fully exercises the Verilog UART module. Please give me some idea of it. After creating the test bench file how to test uart module using testbench. Any suggestions welcome. Thanks in advance...
  6. K

    ISE 9.1i simulaor prob verilog code - help me to solve error

    verilog library module instantiation Hi, I am getting the following simulaor errors while doing behavioural simulaion using ise simulator on ise9.1i. I am running ise tutorial 8 HDLParsers:3482 - Could not resolve instantiated unit ten_cnt in Verilog module work/stopwatch in any library...
  7. K

    please help me to solve error - behavioural simlation ise9.1

    stopwatch Hi, I have copied the stopwatch.v code here, as i could not attach the file. If u find any modifications in this for the simulaion errors as i mentioned earlier please highlight to me. //////////////////////////////////////////////////////////////////////////////// // Company...
  8. K

    please help me to solve error - behavioural simlation ise9.1

    could not resolve instantiated unit Hi All, I am using ISE 9.1i free webpack and trying to do tutorial ISE8 on it. While doing the behavioural simulation getting following errors. I am using Xilinx ISE simulator, please if anybody tried withthis before please help me to solve this. ERROR...
  9. K

    verilog error - ise 9.1i XST sysnthesize error need help

    verilog multi-source error 528 Hi All, I have installed ISE 9.1i free webpack. and running ise 7 tutorial which I downloaded from xilinx website. while doing synthesize using XST synthesizer, I am getting following error, how to solve the error. Please If any of u have run free tutorial on ise...
  10. K

    Need info of MIPS R2000 pipeline design in verilog HDL

    mips pipeline verilog Hi All, I need some information about MIPS R2000 pipeline design I need the information of existing design of MIPS R2000 pipeline using verilog HDL. Please suggest me the website links where i get info about this. I have no idea about this. I am beginner to HDL verilog...
  11. K

    need help to understand diff/comparison betw C & verilog

    Hi All, I would like to know the difference between C programming and Verilog. What are the comparisons can be done between the two. Interms of functionalities/syntax or by considering other features. please write the comparison/difference between these two programming languages Thanks &...
  12. K

    How to write self checking test bench for uart.v

    uart testbench Hi everyone, I am new to verilog Hardware Description Language. I would like to know about writing test bench. I need to write the a self checking test bench that fully exercises the Verilog UART module uart.v The uart.v can be found at the following link...
  13. K

    Need info about Verilog

    Hi everyone, I am a beginner to learn HDL, I need to learn verilog. Please suggest me the good tutorials for it. If anyone having the E books on verilog, please email to me. Any suggestons regarding the Verilg are welcome. Thanks and regards,
  14. K

    How to learn assembly language programming

    Hi everyone, I want to learn assembly language programming. Please send me the websites for the tutorials, or please upload good books if you find. How should i start about it? Do i need to learn assembly instructions for particular microcontroller? Any suggestions are welcome. Thanks.
  15. K

    Information needed for NEC microcontroller

    Hi everyone, Any of you have the experience working using NEC microcontroller? If so please write to me where can i get more information about NEC 8bit microcontroller. I want to know the architectural details, programming, applications. I want to learn the assembly programming for NEC uC. How...
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