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I run transient state simulation in cadence ADE with spectre.
it generated the result in the folder of named : my_test/spectre/schematic/psf/(netlist in :my_test/spectre/schematic/netlist/)
the result file is namded tran.tran.trn.
and I activate the spice explore in the psf floder or elsewhere...
thank you for your advice.
I'm quite sure the bindkey would not be the problem.
my bindkey for instance("i") is "3".
It is not default bindkey.
I write it as "i", in order to underdstandable for others.(default bindkey users)
I am gonna check the CDS.log file.
icfb show up the massegae I...
no response when I enter the key "i" on keyboard
for importing existing cell into current cell in cadence vituoso
layout.
show up that:
*Error* putprop : first arg must be either symbol, list, defstruct or user type -nil.
I need to select layer1 which has two touch edges with layer2
exclude the situation with only one touch edge with layer2.
dose someone have any good idea?
my cadence virtuoso layout editor's F3 key defined as save as
,not the properities of current tools.
Could anyone tell me the function name of F3 key?
it would help me change the save as to tools properities window open
in the bindkey file.
waiting online ...
cadence schematic editor MOS symble netlist generate control
is there any way to generate two different model name for one NMOS symble
in cadence schematic editor on the basis of two different case.
such as, when I run simulation, I take mn for NMOS, when I run layout LVS check,
I take mni for...
I used seperate p+ diffusion for analog NMOS and power NMOS, and I want Calibre LVS to recoginize the two kind of psub, and it don't report softconnect between them.
How to modify Calibre LVS rule file,
I want a critical steps , and idea ...
thanks a lot
waiting for your response.
buck converter startup
I'm a biginner of switch power supply circuit.
The picture buck.jpg is the top circuit.
I want to achieve a 3.3v at vo node.
vob node is referenced at 0.5v, and sent into negetive input of error amplifier,
and the output of amp is compared with ramp siginal to...
I'm a biginner of switch power supply circuit.
The picture buck.jpg is the top circuit.
I want to achieve a 3.3v at vo node.
vob node is referenced at 0.5v, and sent into negetive input of error amplifier,
and the output of amp is compared with ramp siginal to generate PWM siginal.PWM is sent...
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