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Hi,
So you basically removed the second stage? What is ur UGB & load cap?
jgk2004
yeah, but the process we use has an vt around 0.9v at worst corners...
Hi jgk2004
Were you able to meet the commom mode spec of 0-->-.9V with Pmos only input stage?
You can try reducing the parasitic cap at the folding node, which could also help in moving both the zero & the pole..
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