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Recent content by JZJIANG

  1. J

    battery noise v.s switching regulator output ripple

    Hi crutschow, Thank you for your reply and the article provided, and it is very helpful. However, it seems that the article mainly discusses the intrinsic noise of a battery, though the case for 1mA discharging current is demonstrated. In practice, the discharging current of SoC may be very...
  2. J

    battery noise v.s switching regulator output ripple

    Hi all, Which noise is larger in SoCs, battery noise or switching regulator output ripple? The switching regulator output ripple is about several tens of mV at the switching frequency. How about noise at the output of the battery, what is its amplitude and the frequency content? How the bulk...
  3. J

    [Moved]: Low ESL output capacitor for LDO

    Hi, I've just designed an LDO which requires a low ESL output capacitor (1~4.7uF) to offer high PSRR at high frequencies and good transient response. I have completed the preliminary testing with a stacked SMD MLCC capacitor (4.7uF with a resonant frequency at ~1MHz), can anyone give some...
  4. J

    Improve PSRR of an LDO

    Hi, As you have mentioned, we need a higher supply voltage for the control circuit of the NMOS LDO. How can we get the said higher supply voltage, by a built-in charge pump, or by utilizing the existing battery voltage, if possible? Which one has been mostly adopted in practice? On a separate...
  5. J

    Questions on packaging and testing of LDO

    Hi All, I've just taped-out an LDO, and I'm going to package and test the LDO soon. I have several doubts about my subsequent work. I greatly appreciate your kind suggestions and advises. Before I raise my questions, please first have a glance of some specifications of the LDO, Input...
  6. J

    Package and Testing of LDO

    Hi All, I've just taped-out an LDO, and I'm going to package and test the LDO soon. I have several doubts about my subsequent work. I greatly appreciate your kind suggestions and advises. Before I raise my questions, please first have a glance of some specifications of the LDO, Input...
  7. J

    [SOLVED] Analog circuit frequency response analysis with zero frequency

    Your statement "When we get zero frequency in analog amplifier design, we assume that transfer function is equal to zero at zero frequency(because numerator will be zero)" is probably not correct. To my understanding, at zero frequency, the amplitude of the real part and the imaginary part are...
  8. J

    Comments on digitally-controlled LDO

    Thank you for your insightful vision, particularly your comment "Digital control loops can (not to say, always will) be a way to get faster load-step response. But so is using a faster technology to do analog loops." I totally agree with your opinion, and that is the reason I post this thread...
  9. J

    Comments on digitally-controlled LDO

    Thank you very much for sharing your experience, which is really helpful. I guess you are talking about the application incorporating Dynamic Voltage Scaling (DVS) technique. However, I'm a little bit confused about the term "digitally controlled supplies" you mentioned. How does the digital...
  10. J

    Comments on digitally-controlled LDO

    Sorry for any confusion caused. I'm not talking about switch mode regulators vs linear regulators. Instead, I'm talking two categories of linear regulators. "A 100nA-to-2mA successive-approximation digital LDO with PD compensation and sub-LSB duty control achieving a 15.1ns response time at...
  11. J

    Comments on digitally-controlled LDO

    The digitally-controlled LDO has been receiving significant attentions in recent years; in 2017 ISSCC, there is a special session focusing on the digitally-controlled LDO. The presented papers in 2017 ISSCC reveal the advantage of digitally-controlled LDO in low-voltage low-power applications...
  12. J

    Design of Voltage Reference in Deep Submicron CMOS Process

    Thank you very much for your answer. BTW, regarding to the inaccurate modeling you mentioned, are you referring to the vertical/lateral BJTs or the MOSFETs in weak inversion, or both? And what causes the inaccurate modeling in deep submicron CMOS process, could you kindly show me any reference...
  13. J

    Design of Voltage Reference in Deep Submicron CMOS Process

    Hi all, What are the challenges in designing a voltage reference in deep submicron CMOS process? To my knowledge, CMOS voltage reference are designed on the basis of vertical/lateral BJTs and MOSFETs in weak inversion, and they are adopted to emulate the behavior of real BJT. But is there any...
  14. J

    Voltage Reference Measurement

    Hi all, I have several questions on the measurement of the voltage reference. 1. Do I need to design a PCB for the testing of my voltage reference? Can I just put my circuit on the breadboard? 2. What equipment should I use to measure the output of the voltage reference? Can I measure it...
  15. J

    [SOLVED] Current Source with Op-Amp

    The power transistor is NMOS, is it? - - - Updated - - - I know where I am wrong, I mistake the NMOS as PMOS, thank you for your explanation, BTW, could you help me with this question? https://www.edaboard.com/threads/283387/

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