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Hi ,
I am trying to ignore some input /Outputs for comparision.
Tha add ignore output [pin_name] is working fine .
But the same add ignore input [pin_name] is not working the way it should.
when I am reporting for the unmapped keypoints...
The output pin is waived off, but the input pin...
Re: gates in FPGA
No,in the library they dont specify the LUT corresponding to a particulat gate.
Instead its only the change in value of the memory element present in the LUT.
Like a lut of 4 input can have 3-1's and a 1- 0 will behave as a 2 input OR gate
the same LUT with 3-0's and 1-1's...
Re: gates in FPGA
As per Altera and Xilinx Fpga they donot have and, nor gates....The deal every thing in LUT itself...
The libraries Do have And ,Or gate primitives But the final result will be in terms of LUTs.
combinational feedback
If any one can suggest me how to know the exact clock to pad delay through a combinational feedback loop.
]The feedback loop is not inferred but is purposly included.The tool that I am using is XST.
How to constrain So that I will get the delay.
Re: Identifying path
Thanx for the suggestion,
But looking into the rtl viewer will give me just 7-8 pages of gates...
and i might end up with having paths ....that can also me only false one.
If u have done that through rtl viewer then tell me the exact way towards the approach to solve such...
Could any one help me out in this problem..............
Here is the problem...........
I am having a Verilog desing having 5 modules ...instantiated one inside the other.
Now If I want to identify all the paths from the top module to the bottom module how can I do that using Xilinx ISE 8.1i...
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