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Correct. Async latch output changes to match the value of the input after some combinatorial delay (which would be specified in the latch's datasheet).
Certainly. See below. What was happening is the synthesis tool was optimizing away engines 0-5 and keeping engines 6-7. This makes sense because it's getting to the last loop condition for the check of <210 and saying, "Ok, I see condition <210 and that covers all of the other previous 6...
To expand on subbuindia's description, a flip-flop is essentially a "synchronous latch" (i.e. a latch with a clock input and an edge-triggered output). An asynchronous latch is called a "transparent latch" and is level-sensitive rather than edge-sensitive.
In addition, 99% of the time you...
Uhhhhhhh.....how do you think that it's equivalent...?? I'm guessing you're mostly a simulation guy rather than synthesis which might explain it.
The most obvious difference is that the index of [vid_fb_rd_ycoord/30] is going to generate a real-time, non-power-of-2 divider since...
I would expect that they would both synth the same way if you've got a good synth tool. But if they do synth differently I would expect the second version to generate some additional logic or possibly not be able to optimize as much. The first option is the most straight forward approach and...
A few things:
1) That doesn't generate the same logic.
2) You can't synthesize a multi-dimensional port.
3) The parametrization needs to be done with a for-loop, not with another module.
But thanks for trying. Any other takers?
I have the following combinatorial code block:
wire [6:0] vid_fb_rd_data_gen [C_NUM_ENGINES];
logic [6:0] vid_fb_rd_data;
wire [8:0] vid_fb_rd_ycoord;
always_comb
begin
if (vid_fb_rd_ycoord < 30)
vid_fb_rd_data = vid_fb_rd_data_gen[0];
else if (vid_fb_rd_ycoord < 60)...
Re: Modelsim error code 211 : segmentation violation..What t
I got this same error and came here looking for answers. This error is not necessarily a license issue. For instance, I knew my license was good so it had to be another issue. I didn't find any help at all on Google but I finally...
I need to make the subject line a bit more specific:
"How to instantiate a SystemVerilog netlist (with an interface at the top-level) inside of a Verilog-2001 module".
I have an SV design that has an interface at the top-level as follows:
module my_design_top (
//more ports...
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