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hi every one
i'm trying to get timing report with report_timing in DC and the outcomes are like follows:
how can i get maximum delay between all my inputs and all my outputs, i thought report_timing or report_qor will give me critical path, but as i have shown above DC report wrong critical...
hi ads-ee
my combinational logic comprise of some arithmatic likes multiplication, adder, sub , i think these functions have comparable activity factor with these 8 flip flop. besides my lookup logic is much larger than regout logic, and i think its glitch activity is much higher ??!!
hi every one
i have a simple design named "hardenSBox" comprised of two parts 1)sequential part, so-called "regOut" which has 8 DFF 2)combinational part so-called "lookUp". i haved showed in following section, verilog code related to each part:
module...
my second problem solved, i just changed set link_library ./db/NangateOpenCellLibrary_45nm.db to set link_library [list * ./db/NangateOpenCellLibrary_45nm.db] ?? actually i don't know why it solved but it worked
This is a new problem resulting from fixing the problems in this thread.
i have all of these names n?? and U?? in my netlist, the question is when i apply top-down approach for syntheses i didn't had these problems , how can hierarchy names have changes when i change my synthesis method ??
the...
hi Dear ads-ee
my problem solved , actually the problem was not about lookup module(combinational part) , i dont know why regOut (sequential logic) work incorrectly after syntheses , i try to change of used flip flops form SDFF to DFF and also add sttribute 'set_dont_touch' for signal reset of...
really sorry, you are right i should have explained more precisely
my design structure is like this:
Sbox is top module and contains two other modules 'lookup' and 'regout'
i first synthesis lookup and post simulate it and everything is right and this is a piece of synthesis file by DC
module...
when we synthesis bottom-up approach , don't we expect each module just sit in upper module exactly ?? first code is synthesis of lookup in context of upper module :
module lookup ( indexX, indexY, intermediate );
input [3:0] indexX;
input [3:0] indexY;
output [7:0] intermediate;
wire...
i get your point, but i did nothing wrong in my design, i don't have any multiple drive point in my design, i have checked design and these X are created at the end of lookup module after some nanagate (all nandgates inputs are correct and stable), then how it is possible ??
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hi
i came across something, i think my second design signal strength have been changed somehow and it is the cause for the problem , i have attach two picture of that are simulation results of module lookup alone ( the correct one) and simulation result of module lookup in second scenario (...
hi
i came across something, i think my second design signal strength have been changed somehow and it is the cause for the problem , i have attach two picture of that are simulation results of module lookup alone ( the correct one) and simulation result of module lookup in second scenario (...
i did all of these and i traced X back to output of lookup module (combinational logic) but i couldn't find out why ? all output nets of lookup have some valid values before end up to nana gates " because i used NandGateLibrary" , and question is what could possibly goes wrong in nand gates ...
i changed my code to lower case , my problem is not with syntax error at all,
and about hierarchy, i just set attribute "set_dont_touch" for each one of my instance in top module and i could exactly separate each module
the problem is : i googled that set_dont_touch attribute cause DC don't...
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