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Recent content by JulianCas

  1. J

    PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    @ads-ee, I did test the probes first thing when I faced the issue and were working, perfect square wave form at 1M. :sad: @SunnySkyguy, It is a good tip to consider transmission line effects but in my case did not see any difference. I am currently using a development and educational board and...
  2. J

    PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    Unfortunately that's the only oscilloscope I have right now. I checked the GPIO schematics and I am getting the signals and grounds properly connected. The only thing I noticed is that it says VCC instead VDD which according FvM comment, not sure if they made a label mistake or definitively...
  3. J

    PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    @FvM, My scope has a BW 100Mhz, not sure if a frequency of 18Mhz is not able to handle it. However, the way I am measuring the signal is not directly to the pin of the codec but assigning the pins to GPIOs of the FPGA like this: GPIO_0(10) <= AUD_ADCLRCK; GPIO_0(0) <= AUD_BCLK...
  4. J

    PLL altera IP Core design of 18.432Mhz, output waveform is not as expected

    Hi, I am using altera IP core PLL with the setup shown in the image. When I check the waveform in the scope, I have got a sine wave of 2 vpp with a DC component of 1.5 v. The issue here is that am using that clock to sync with the Audio codec WM8731 for I2S communication but it seems that...
  5. J

    [SOLVED] FPGA IP cores used in production, Any royalties involved?

    Hi All, I have read many forums where it is advised to use IP cores instead implementing it depending on the case, for instance PLLs or High Speed interfaces like USB SS or 10G Ethernet, etc. My background is EE but also in the computing engineering field I could noticed that the same advice...
  6. J

    [SOLVED] If-else statement in process is not working with multiple inputs in sensitive list

    Hi all, Thanks for you reply and I got your point. I was trying to check each state machine by lighting one LED per state which does not mean anything. It worked when I used toLed <= "0000" but I needed to re-design the process understanding the way combinational and state memory processes work.
  7. J

    [SOLVED] If-else statement in process is not working with multiple inputs in sensitive list

    Hi, I was trying to implement a finite state machine, and I started using If else statement, then I realized that no matter the condition, all were met which was not expected, I was expecting only one. Then I tried using the case control and it worked. The following example is a simplified...
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