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Recent content by juggernaut

  1. J

    How can I get 2M CLK signal from 19.44M Overhead signal?

    and in response to Davis - if there is already a 32.768MHz clock available then there is no need for any DLL/PLL or clever digital circuitry. Divide by 16 (only takes a few flip-flops) and you have your 2.048MHz clock. I assume this query arises because there is no easy multiple of 2.048MHz...
  2. J

    How can I get 2M CLK signal from 19.44M Overhead signal?

    Hi all. There is obviously no way derive a clean, jitter-compliant 2.048MHz clock from a 19.44MHz clock in the digital domain. You need an external PLL. However, if you think about what you need the clock for then it may turn out that you don't need actually need it. For example, if your...
  3. J

    X_linx ISE 6.1i Problem - bad nph file

    Re: X_linx ISE 6.1i Problem I have to agree with AndrewC - my somwhat limited experience with XST is that it's a piece of junk. If you access to another synthesiser I would suggest giving that a go...
  4. J

    What's the max frequency Xilinx FPGA can run?

    200 mhz xilinx fpga My experience has been that you can design large and complex designs to run around 200MHz if you are very careful with pipelining and so on. You can certainly push beyond this to the 300MHz mark for simple circuits but you don't get more than a layer or two of combinatorial...
  5. J

    How to decrease time slacks in Synplify Pro?

    Re: Synplify Pro timing Remember that Synplify is just making an estimate of what the timing will be - it's not until you run it through the FPGA vendors PAR tools that you get the definitive answer. Has the PAR timing changed across the revisions? Also, if you are targetting a new FPGA/PLD...
  6. J

    Virtex-II pro Dev board - looking for schematics

    Re: Virtex-II pro Dev board Xilinx give away the schematics/layour for at least one of their dev boards. Go to... https://www.xilinx.com/xlnx/xebiz/board_search.jsp Select "Virtex2-Pro Boards", and then the ML300 board (not the version with Windriver). There are schematics and layout...
  7. J

    different results from leonardo and fpga express

    That message normally appears when you don't assign the signal under reset...
  8. J

    padding to ethernet using fpga

    err, sorry. I just re-read your post - you are adding more data to the existing PDU, so the length field will have to change to reflect this new data. Depending on the amount of data you add, the amount of required padding may decrease or increase to satisfy the rule...
  9. J

    padding to ethernet using fpga

    The rule is that pdu_length+pad+trailer = a multiple of 48 (the number of payload bytes in an ATM cell. Since, for any given PDU, the length is fixed, and the trailer size is fixed (8 bytyes from memory) it is an easy exercise to determine what the pad length should be (it will always be between...
  10. J

    Problem programming VirtexE in ISE 5.2

    I think the mask is only used for verification, so if you deselect "verify" when you go to program the device it might work. The .msk file is created when you do bitgen - make sure it is in the same directory (and the same name as) your bitfile when you program.
  11. J

    Help needed for timing problem with Xilinx ISE

    defining timings xilinx ise I couldn't agree more Maestro - records, funtions, generics and other advanced stuff are all very useful and powerful when used properly and are easily synthesised, provided you know what you're doing. There seems to be a strongly entrenched attitude in the...
  12. J

    Help needed for timing problem with Xilinx ISE

    actual period xilinx I have to disagree with Bartart (above) though - "Generic" is very uesful in synthesisable code, and should be used to make entities more general purpose. For example, the above code that I've posted could have any delay at all, and the resource utilisation would scale to...
  13. J

    Help needed for timing problem with Xilinx ISE

    xcs10 project Your problem is definitly (and as mentioned above) that your code is not synthesisable. Effectivly you have mixed "behavioral" and "synthesisable" VHDL, and whilst it will work fine in simulation, it is not reproducable in reality. How does "after" relate to gates and flip-flops...
  14. J

    What to choose for DSP design? Xilinx or Altera?

    Spartan2 is the equivilant of Virtex, Spartan2e is the the equivilant of Virtex-E, and the new Spartan3 is the equivilant of Virtex2. So the answer is yes, anything you can do in a regular Xilinx device you can do in a Spartan. You just have to be aware that the Spartan equivilants don't have as...
  15. J

    How can I implement a asyn ram in Xilinx ?

    xilinx fpga ram It's been many years since I used async RAM, so I could be way off the mark here, but can you not make the Xilinx distributed ram (sync write/async read) look like async RAM by driving the write clock input with your write-enable signal instead of a clock? I mean, even async ram...
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