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I am pursuing M.Tech in VLSI design and have designed a pipelined Cordic based NCO but i am having glitches in my output. This is a part of my m.tech thesis and i will have to complete very soon.
It will be of great help if someone kindly helps me sort out my problem. i have attached the program...
i am using all digital pll, so am using NCO. now i have designed two types of NCO, one using LUT and other using cordic algorithm which is controlled by a digital word(14 bit). This is why i need an ADPLL which will analyze and compare these two types of NCO. So i have selected an architecture...
thank you so much FvM, but MSBR, as you are telling you use Xilinx ISE, i am using the same xilinx 14.7 but it doesnot instantiate dual port ram. My target device is virtex 4 sx35 ff668. Might be this doesnot support dual port ram
thank you all for your valuable response. I have already implemented the LUT with scaling factor and then converting to binary representation. Now I have 90 degree symmetry. and I have to generate sine and cos wave simultaneously at the same clock. I have only one LUT. which means I have to...
I am designing an ADPLL but am not getting which phase detector to use.
EXOR gate phase detector
JK Flip-flop phase detector
Digital phase frequency detector
DETDFF
moreover there remains a TDC along with it , but some papers tell that TDC alone is sufficient.
please help me understand what...
thanks for your reply but can you tell what is the +Q0.14 format and how to use it?
moreover it will be verymuch helpful if you explain the procedure to generate a rom and store a text file. thats what i have also been trying, but i see it stores hex values.
I am new in verilog but am getting used to it. My problem is how to store amplitude values of the sine wave. i am using a 14 bit resolution which means i have 2^14 no of values between 0 to 360 / 90 (doesn't matter) of sine. now the address will be linear but the corresponding sine amplitudes...
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