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Hi Permute,
do you mean like this? I made a few changes though (but not many)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL...
Hello everyone,
I'm trying to implement a simple RAM (for the SP601 evaluation kit) that will store a 12-bit data. I've seen many sample codes from XST user guide such as this one
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library...
Yes that's what I mean...but is it the same when I use rising_edge (signal) or falling_edge (signal)?
I guess there can only be one rising_edge or falling_edge in a process...isn't it? Does that imply that if I want to detect a rising or a falling edge of another signal I can use that syntax if...
What is the meaning of a VHDL line like this :
if (signal = '1' and signalx = '0') then
and what is the difference when the values above are interchanged? (signal is 0 and signalx is 1)? I've seen some codes using that line but I haven't gotten the idea of that line...could someone explain...
if start='1' and start_dly='0' then
Could you explain what is the meaning of that line? I've seen codes using that lines...and what is the difference when it is
if start = '0' and start_dly = '1' then ??
Thanks and regards..
Juan
Thanks TrickyDicky,
Yeah I managed to fix the problem and omitted the fixed point converters and now they're showing results....
And if I may ask you a question, which bits should I take? now I'm taking the 12 LSBs and they have different results for each inputs compared to when I take the 12...
Hi everyone,
I'm making a code that receives a signal that has higher value than a comparator. If that condition is correct, a trigger will have a '1' value. This value is another condition to transfer the input to the output. However, before transferring, the input signal should be multiplied...
So how can I use the library (putting the code into my file is wrong, right?)? The errors are pointed to my main file, saying that the std_logic is not declared. However, those warnings are gone if I remove the new library code. Are the libraries are automatically used?
Actually I have included the std_logic_1164 library...so in my library declaration I put this
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library IEEE_PROPOSED;
use IEEE_PROPOSED.fixed_float_types.ALL;
package fixed_float_types is
-- Types used for generics of fixed_generic_pkg
type...
That's OK...
But which source code do you mean that I should include in my project? is it the one that has only these lines?
-- --------------------------------------------------------------------
-- "fixed_float_types" package contains types used in the fixed and floating
-- point packages...
I have downloaded the source codes for the Xilinx 11.1 (though I'm using 13.2) and followed the instructions within the documentation....however I still couldn't use the proposed library and now in my project hierarchy there's a folder icon named "Unassigned User Library Module"...how can I use...
Yes TrickDicky,
When I'm operating with floating points it is taking large resources of the FPGA I'm using....well, fixed-points it is...
---------- Post added at 13:37 ---------- Previous post was at 13:34 ----------
Yes TrickDicky,
When I'm operating with floating points it is taking large...
Currently I have to use the numbers like 0.1, 6.51E-5 and such as my multplier/comparator therefore I have to do fixed to float and then float to fixed as the output...but I was wondering, can I directly convert my 12-bit signal into a floating-point since it's possible to customize the integer...
Hi Shan,
I also had the idea of concatenating but again I also told myself that maybe I have to change that to a floating point-again....
So is it better to convert the floating-points to fixed points (in terms of easiness) and then from the fixed-points I take the 12-bit LSBs again?
By the...
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