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Bandgap in SOI
Hi,
Has anyone tried for bandgap on SOI?
how are the results (variation percentage of bandgap voltage)?
kindly f/w any docs regarding this.
thanks in advance.
regards,
JT
agree with dick_freebird. Maintaining high psrr at VCO frequency is simply not practical with limited Iq of LDO. Such things need to be taken care at system design level.
Hi,
20nH ESL and load varies at the pace of 0.1ns!!!! i think you need to reduce ESL by very good amount, else there would be no regulator action.
regds
JT
low noise band gap reference
Thaks eriki,
i have gone thru this datasheet.
but the current consumption is very high....prohibitively high...
regards,
JT
what do test chips do
First thing that everyone should do is to check if the IC heats up as soon as the power is on for the first time.
if it heats up, first suspect the PCB.
This heating will spoil the IC and you can never check the functionality thereafter.
nmos dnwell
I think all points are covered by others.
But one must understand that nwell & DNW are shorted.
So if some bulk of pmos is at different potential, then that should have not be put under the same DNW. bcos nwell is connected to VDD and nwell and DNW are shorted to VDD.
So PMOS...
low noise bandgap
Is it possible to design a very low noise bandgap reference?
(without using any RC filter).
Will it help using a chopper?
say 20-30uV rms in 10hz to 100kHz.
thanks in advance.
JT
Re: How to deal with the layout of a circuit with large curr
Please make sure the metals are wide enough not only to satisfy the EM checks but also the IR drop on the routing. if there is space constraint you can route it on more than one metals but make sure you put enough vias b/w diff metals.
ldo compensation
Hi,
I am looking for methods of compensating LDO "INTERNALLY".
This has a external Capacitor of 1uF.
any knowledge sharing in this regard would be useful to me.
regards & thanks in advance,
JT
bjt n well
Hi,
I want to put BJT in DNW like i have done for other mos transistors. It is Vertical PNP type BJT.
the moment i put the BJT inside the DNW, the transistor is not detected in LVS run.
what is the solution for this??
Did anybody face the same problem?? how did you solve it...
Thanks Leo & K_90 for your inputs.
I simulated using a separate PAD for switching and silent circuits. It works However, when connected at the top level, still there is noise coupling.
Should I use a altogether separate power supply pin for BGR?
again thanks for your inputs.
regards,
JT
How to isolate on-chip sensitive circuits like BGR from switching circuits which switch at 100MHz but with package inductance create Very high frequency noise?
Can we use a onchip inductor to decouple the switching (noisy) circuit and the supply sensitive circuit?
any idea/document/links etc...
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