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Recent content by jsathish.challenge

  1. J

    [SOLVED] delay value differ in same cell

    Thanks it clarify my doubt
  2. J

    [SOLVED] Number of CORE in asic chip

    Thanks for your inputs,so apart from the wire length increased due to logic spreading,is there any other reason is there to make, the physical design engineer work to be difficult
  3. J

    [SOLVED] delay value differ in same cell

    Hi all, In our .lib ,for example for AND gate has 2 inputs.It has below arcs A-->X B-->X I have a one doubt on the cell delay value,why the cell delay is different between A to X and B to X for same slew and load.... Regards, sathish
  4. J

    [SOLVED] Number of CORE in asic chip

    HI all, I Gone through some of the design..And i am working on physical design currently.What sort of complexity the physical design engineer will face,if number of processor is increased.for example what is the challenges if i have 2 cpu cores instead of 1 cpu core in my design,how it really...
  5. J

    They say static IR drop causes SI noise and delay.

    If you have less voltage is applied to the VDD pin of the cell,then the noise margin also will getting reduced.(Because VIHmin get reduced and VILmax also increased) .Because of this there is a possiblity that crosstalk noise can increase.I hope this will help... Regards, sathish
  6. J

    Why cell delay is different between two arcs for same slew and load?

    Hi all, In our .lib ,for example for AND gate has 2 inputs.It has below arcs A-->X B-->X I have a one doubt on the cell delay value,why the cell delay is different between A to X and B to X for same slew and load.... Regards, sathish
  7. J

    please recommend any good books on power planning

    i want a good book on designing power structure for the ASIC in physical design area not in PCB design
  8. J

    please recommend any good books on power planning

    When before developing power structure for an Asic we need to plan or give up with power strategy,that is how to design the power structure.For this we need to consider so much physical effects and package characteristics,so to learn this things,like this is there is any good books are there ?
  9. J

    please recommend any good books on power planning

    hi, can you recommend any good book on power planning regards, sathish
  10. J

    process of 1 in .lib means?

    In .lib ,what is mean by the process=1 ,i am seeing for strong corner and weak corner both having same value as 1? regards, sathish
  11. J

    NLDM driver model in cell characterization

    In Nldm driver model the Rd represents what resistance physically,whether on resistance or some thing else?.And how this resistance will smoothen the ramp transistion to exact curvature seen in real waveform regards, sathish
  12. J

    buffer driving distance

    hi, How to find the capacitance of the net of unit distance in particular technology(in um)
  13. J

    buffer driving distance

    Hi all, How to find the distance a buffer can drive ?. Suppose my buffer drive strength is 12x. and output capacitance is 10pf .and a unit net capacitance of a technology 2Ff. regards, sathish
  14. J

    Skew in prects stage is modeled as 0ps

    Hi to all, In my design the skew is set as 0ps for pre CTS constraints.Why they always set the skew =0ps .
  15. J

    static signals needs to set false path

    Hi all, In my design i have scan flipflop contains sd(set),rd(reset),clk,si(scan input),q(output),d(signal input).sd(tied to 1) For static signals like SD and all other static signals how the tool taken care when the Timing closure stage.whether it is taken as a falsepaths?.
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