Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by joul

  1. J

    Xilinx CoreGen core in ISE 14.7: sim OK but synthesis is instantiating empty module

    Hello, I already asked this question in Xilinx forums, but have not received an answer yet... Maybe you guys can help me! I'm trying to instantiate a floating point 5.0 core generated by 'Core Generator and architecture wizard'... In my ISE 14.7 project (targeting xc6slx4), I did Project ->...
  2. J

    Is that considered a combinatorial loop and how bad is it ?

    To clarify, s2 is set on power on, so everything should be fine right ?
  3. J

    Is that considered a combinatorial loop and how bad is it ?

    That's the point, it should never go back to '0' once it goes to '1'. Is this logic safe or not ?
  4. J

    Is that considered a combinatorial loop and how bad is it ?

    Thanks for your answer. So the fact that s1 is part of the condition in its own assignment is not a problem ?
  5. J

    Is that considered a combinatorial loop and how bad is it ?

    Let's say we have entity ent is port ( ... ... a : out std_logic ); end ent; architecture archi of ent is signal s1,s2 : std_logic; begin ... s2 <= <some condition>; ... s1 <= '1' when s2 = '0' or s1 = '1' else '0'; a <= s1; end archi ; Basically I want a to go to...
See more

Part and Inventory Search

Back
Top