Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by joskin

  1. J

    What are the layout techniques used?

    Re: Layout Techniques What's the meaning of PLI?
  2. J

    The problem in the clock generator of MASH sigma delta ADC

    Hi, I'm designing a MASH sigma delta ADC. As you know, if transistor-level clock generator is included in the simulation netlist, the running time will be long. So I used a behavioral clock generator before, and the simulation results show the performance is what I expected. Unfortunately...
  3. J

    The problem in the clock generator of MASH sigma delta ADC

    Hi, I'm designing a MASH sigma delta ADC. As you know, if transistor-level clock generator is included in the simulation netlist, the running time will be long. So I used a behavioral clock generator before, and the simulation results show the performance is what I expected. Unfortunately...
  4. J

    how to check the stability of SC CMFB ?

    Re: SC CMFB Is it true that the SC CMFB doesn't add pole to the loop?
  5. J

    Sigma delta modulator for different applications

    Sigma delta modulator has been applied to audio signal processing, vedio signal processing and DC measurement. Many papers about SDMs applied to audio signal processing have been presentd. But I found few papers about DC measurement. Can anyone help me?
  6. J

    How to design the OPAMP used in 1-bit sigma-delta modulator?

    I'm designing a 1-bit sigma-delta modulator. I find the differential voltage at the OPAMP input is greater than √2 * (VGS-VTH) at the begining of integration phase, which is caused by the big difference between input voltage and feedback voltage. As you know, this will cause slewing, and hence...
  7. J

    How to simulate the stability of SC CMFB loop in a full differential OPAMP?

    Re: SC CMFB stability? Thanks! One more question. Because the OPAMP is applied in a SC integrator, how to model the external SC when running the simulation. Replace the SC by resistor?
  8. J

    How to simulate the stability of SC CMFB loop in a full differential OPAMP?

    How to simulate the stability of SC CMFB loop in a full differential OPAMP?
  9. J

    Hspice oscillation issues in LDO design

    Re: hspice error (?) I think it's a stability problem. Although you said the PM is 70, perhaps the setup is something wrong when running simualtion.
  10. J

    how to simualte CMRR for diffrential amp?

    cmrr vcvs I think derekqiao is right!
  11. J

    Questions about Class D Power Amplifier

    Re: Class D Power Amplifier? But how about the current path?
  12. J

    Questions about Class D Power Amplifier

    Class D Power Amplifier? Did anyone designed class-D power amplifier with CMOS process? Will the current flow through the parasitic diodes in MOS ? What advantage does the DMOS has?
  13. J

    OCP,OVP & OTP in high power amplifier?

    I designed a class D power amplifier in CMOS process, which is applied in audio band. Its current is up to 100mA. I heard Over-Current-Protection, Over-Voltage-Protection and Over-Temprature-Protection mechanism should be designed in such high power amplifier? Can anyone share any experience...
  14. J

    About Verilog-A and SpectreHDL?

    spectrehdl What's the difference and relation between Verilog-A and SpectreHDL?
  15. J

    How to look for zero point and dominant ploe in AC analysis?

    Re: How to look for zero point and dominant ploe in AC analy Hi,Layes2: What's the incorrect pairs of poles and zeros means? Do you think the simulation result is not correct?
See more

Part and Inventory Search

Back
Top