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Recent content by joseph1991

  1. J

    autonomous wireless controlled car

    Hi, I have a project for school (autonomous wireless controlled car) and I have to imagine a detailed block diagram for this Using a few signals including car position (x,y), obstacles position and final destination I have to control the car to arrive at destination. I mention that I use an...
  2. J

    [SOLVED] signal with a length = 2.4ms and a frequency of 2.4kHz on FPGA

    it works !! thank you !!
  3. J

    [SOLVED] signal with a length = 2.4ms and a frequency of 2.4kHz on FPGA

    thank you for helping me but the code is not synthetizable same error
  4. J

    [SOLVED] signal with a length = 2.4ms and a frequency of 2.4kHz on FPGA

    Hi I wrote some code for a school project and when Iwant to sythesize the code this erro appear [I] line 37: The logic for <sunet> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software...
  5. J

    verilog code for a frequency multiplier

    i really need to know if is possible to multiply a clock frequency in verilog or maybe someone can explain me how to delay a clock signal with a quarter of a period
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