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Recent content by jojo12

  1. J

    VHDL code - Can't resolve multiple constant drivers for net 'a'

    If anyone can help it would be greatly appreciated. I can't figure out how to specify a in the code to not get the error. I'm getting this error for all a's (a(3), a(2), a(1), a(0)) library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity counter is port (x : in...
  2. J

    Need help on VHDL code for a 4 bit counter. with Error (10327): VHDL error at counter.vhd(26): can't determine definition of operator ""<"" -- found 0

    In my class, in slides that is how we write if statements in Quartus. It won't work without it.
  3. J

    Need help on VHDL code for a 4 bit counter. with Error (10327): VHDL error at counter.vhd(26): can't determine definition of operator ""<"" -- found 0

    Yes sorry, the error is at the line where it says "if D<9 then"
  4. J

    Need help on VHDL code for a 4 bit counter. with Error (10327): VHDL error at counter.vhd(26): can't determine definition of operator ""<"" -- found 0

    Yes sorry, the error is at the line where it says "if D<9 then"
  5. J

    Need help on VHDL code for a 4 bit counter. with Error (10327): VHDL error at counter.vhd(26): can't determine definition of operator ""<"" -- found 0

    -- Counter1bit Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter1bit is port( D, clk, clr : in bit; -- input Q: out bit ); -- output end counter1bit; architecture behavior of counter1bit is begin process (clk,clr) begin if clr <=...
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