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dear thanks.yes those all are primitive.and now i have complied it and got just one warning.its ok.
now problem is how i can generate its test bench in xilinx. if someone have prepared test bench for async FIFO.plz send
or
tell me how i can genrate it in vhdl
tks
dear thanks.yes those all are primitive.and now i have complied it and got just one warning.its ok.
now problem is how i can generate its test bench in xilinx. if someone have prepared test bench for async FIFO.plz send
or
tell me how i can genrate it in vhdl
tks
Dear during compilation of "implementation of asynchronous FIFO implementation in vhdl" program the following components are missing..
BUFGP
MUXCY_L
RAMB4_S8_S8
Plz send me vhdl program of those components.
And plz also tell how to incorporate those programs so that I am able to run my...
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