Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
LDO question
for the 2nd issue. the resistors will be proportion,maybe you simulated the LDO with BandGap. The output voltage of the bandgap change, so the LDO's output will be changed
dbc jitter
you can integrate the area under the double-sideband phase noise curve,over a specific bandwidth to obtain the root-mean-square jitter
Added after 11 minutes:
there is article by neil roberts
it will be helpful to you
The issue is solved when i used command "includeFile" to specify the model path ,and the correct design name is *.C and include netlist file *.S . it different from that in spectre
i used Hspice to simulate in ocean scipt
but the error message:
Invalid command modelFile for simulator 'hspiceS'
i use the command modelFile to specify the corner model
but failed
anyother tell me the right way to specify corner files ?
the nonideal effects in charge pump produce the spurs, usually harmonious of the compare frequency.the effective means to reduce the spurs is to eliminate or alleviate the nonidealities.
Re: PLL Loop bandwidth
I think
wn=sqrt(Kvco*Icp/N*C1)
wn is natural frequency, N is the divider ratio, Icp is charge pump current, Kvco is the gain of the VCO.
and wc=1.55wn
w-3db=2.06wn
wc is cross frequency in the bode plot
w-3db is the closed loop -3dB bandwith
Re: PLL noise
the pll noise is phase noise
named phase noise because the noise effect the phase of the output signal
the sub blocks of the pll has its own noise
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
