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Recent content by Joel_Damato

  1. J

    Verilog beginner: is synthetized rtl optimal?

    Thanks Dpaul, I am just tinkering with the tool, throwing random code at it..
  2. J

    Verilog beginner: is synthetized rtl optimal?

    You are right. Overlooked that. Here is the corrected code and the new synthesis: module top(input clk, input led, output led2, output to_port1,output [24:0] to_port2); reg ctr = 0; reg[24:0] counter = 2; always@(posedge clk) begin if (ctr == 1) begin ctr <= 0; counter <=...
  3. J

    Verilog beginner: is synthetized rtl optimal?

    Hi, For that source code: module top(input clk, input led, output to_port1,output [24:0] to_port2); reg ctr = 0; reg[24:0] counter = 2; always@(posedge clk) begin if (ctr == 1) begin ctr <= 0; counter <= counter + 1; end else ctr <= 1; end assign led = ctr...
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