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One more tool for circuit debugging via JTAG/boundary-scan is TopJTAG Probe **broken link removed**. With TopJTAG Probe it is possible to view pin states (i.e. it works like slow logic analyzer) and to control pin states to check interconnects, light LEDs etc.
sample only bounday scan cell
There is no bug in urjtag or TopJTAG Probe. The problem is the BSDL only valid for a pre-configured device and must be modified to used with a configured device. On a pre-configured device each bidirectional pin has 3 associated boundary-scan cells (input, control...
actel post program bsdl
* It is not my text, I've just copy-pasted a comment from the BSDL file which answers your original question. This line was a part of that comment in the BSDL file.
* Just decided to add some more explanation:
Usually a bidirectional pin has 3 boundary-scan cells...
boundary scan cell in fpga
I found the answer inside the BSDL file:
-- This BSDL file reflects the pre-programming JTAG
-- behavior. To reflect the post-programming JTAG
-- behavior, edit this file as described below:
-- If the I/O is unused or configured as an output,
-- the input boundary...
boundary scan & output input
You can try to watch pin states with another boundary-scan tool -- TopJTAG Probe **broken link removed**. It's a GUI software and therefore more easier to use then urjtag.
If you still have a problem, please, share a link to your FPGA BSDL file. So we can see what...
BGA chips usually has a JTAG interface so you can use boundary-scan tools to test PCB interconnects. I'd recommend Scanseer software for this purpose. Scanseer can probe and even control pins of any part with JTAG.
jtagsel
It looks like setting JTAGSEL to high puts AT91SAM7S64 core into a reset state. Is it a valid behavior or I have some problems with my pcb/hardware?
I would like to monitor and manipulate with signals on AT91SAM7S64 pins to do some board testing using a boundary-scan software. So I set...
Re: Testing FPGA board
Try to use boundary-scan software like Scanseer to probe (and toggle) FPGA pins. Scanseer can record waveforms for FPGA I/Os, so you can see how your communication signals running.
cpld/chipscope
Try Scanseer. It's a boundary-scan software like ChipScope, but it works with any chips that supports boundary-scan, not only Xilinx FPGAs. So it should work fine with your CPLD.
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