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Dear all,
I need to use multiple-steps compilation in nc-sim with dumping out the fsdb file. I failed to use
....
call fsdbDumpfile ("xxx.fsdb")
call fsdbDumpvars 0 top_xxx_module
run
....
in command.tcl for the -INPUT option in ncsim.
The log file shows the following:
ERROR: VHPI...
Hi SPIL experts,
I met a problem about writing a spf.
1. During the initial stage, the test clock pin is required to set at 1'b1 for serving as a control signal (like reset), and then become to 1'b0 after a period of 5000ns.
2. After the reset is done, the test mode can only be...
[DFT & Tetramax] Questions related to STIL DFT protocol file
Hi SPIL experts,
I met a problem about writing a spf.
1. During the initial stage, the test clock pin is required to set at 1'b1 for serving as a control signal (like reset), and then become to 1'b0 after a period of 5000ns.
2...
Dear all,
The problem I met is I don't know how to do the ATPG at the chip level since I do the dft in the sub module.
Thus, the reported .spf is for the submodule instead of top module. But when doing ATPG, isn't it based on top level module to create patterns for the whole chip?
If I do the...
To be more precise, I need to use multiple-steps in NC (ie. using ncvlog, ncelab and ncsim) to do the simulation.
In ncverilog, i can use -f design_filelist and -v library files to simulate. But I don't know how do use multiple steps in NC.
Thx.
Hi,
I'd like to include many design files into compilation with some library files.
Could anyone show me a quick example in its command line?
I wanna to integrate the simulation into Makefile. Any example is much appreciated.
Thx a lot.
Dear all,
For some reasons, i can't do the balance clock tree in back-end. Instead, I need to balance in synopsys dc_shell. My problem is:
There are two cpu clock domains, clk1 and clk2, both running at 25Mhz. They are from the same source, clktop, but have different control due to some power...
Dear all,
When I do the synthesis, synopsys seems changing some instance names for those modules which are referenced from a library. Could I fix the name in netlist to whatever I used in RTL?
Thx.
Dear all,
I've met a problems of inserting scan chain in a top module, A with instances of module B and C.
How do I do the scan chain to generate a final complete script?
Do I generate a sub script for each sub module of B and C, respectively and then generate a top script for top module A...
Dear all,
Currently I need to maintain a old testbench which uses parameter for the test program's path and the test filename.
I need to complete a regression which requires to automatically change the path and file name of those test programs.
So far, I get the info about deprecated defparam...
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