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Hi.
I have a ASIC design that I made staged mesh grid pattern on a mettle layer for ground on one mettle layer and now when I try and extract the design with full LRC parasitics it is to big to simulate. i.e. the caliber view alone is ~2G if the system can generate it. I have tried enabling...
Thanks I am probably doing dumb things here as mentioned above. This is no so much a memory bank for say as a bank of control registers. The reason I am outpointing the whole thing is I was having trouble a wile back with control registers not being written in some sub blocks. Therefore I...
Sory I am terrible at giving details..
the oringanal long way of doing it is as follows :
entity control_registers is
Port ( clk_40 : in STD_LOGIC;
reset : in STD_LOGIC;
wr : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (15 downto 0);
address ...
Hi
I have been trying to make a clean variable size memory bank with little to no success.
What i am trying to replace is the classic case statement :
process(clk_40,reset,wr,data,address)
begin
if clk_40'event and clk_40 = '1' then
if reset = '1' then
registers_int <= (others =>(others...
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