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Can anyone help spot what's wrong with this code, or are my expectations wrong? I tried to create a register file where I could write to any two addresses (out of 16) synchronously, and read any two addresses anytime. Here's what I have:
module mod_regfile (
input wire clk, // write...
Using Libero's SmartGen tool, today I created a 16-bit Brent-Kung adder/subtractor. I pasted the resulting Verilog code into an ALU module and ran a few (10) tests against it. It ran fine. And the result was a LOT smaller than the one synthesized from pure behavioral Verilog. :-)
But when I...
I'm doing a simple Logical Unit module with a few logical functions working on 16-bit values. I want to trigger this logic with a statement run off clocked logic in another module... so I put a "strobe" input and made that the only thing that triggers:
module mod_logic_unit (
input wire...
As part of a larger project, I am trying to model a memory subsystem and am having trouble. It's a static async SRAM with an 8-bit bidirectional IO port.
The SRAMs are loading their images from the input files properly. The values when the 'A' (CPU) side is writing are being saved in the SRAM...
As part of a larger project, I am trying to model a memory subsystem and am having trouble. It's a static async SRAM with an 8-bit bidirectional IO port.
The SRAMs are loading their images from the input files properly. The values when the 'A' (CPU) side is writing are being saved in the...
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