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Hi mate,
In calculations currents through branches are approximated to be the same. As you can see in your case, there is 30% difference between them. Therefore, circuit is not operating ok. First, try to increase widths and especially lengths of all transistors. These bottom one have to be...
You are limited by the oxide breakdown, which usually appears when Eox=Vox/tox reaches 1 V/nm. Here Eox is electrical field across the oxide, Vox is voltage (higher of Vgs and Vdg) and tox is oxide thickness in your tech (somewhere between 2-3nm I guess). Therefore, for Eox<1 V/nm you are...
In your analog environment go to outputs/setup, name power somehow, open calculator tool, make an expression and use it. In calculator you can built almost everything you need, I think in your case you need average(Vdd*Idd). You want to measure power consumption of your control? For input/out...
Hi Jay,
These spikes are related to coupling capacitance between the input and the output of the inverter (Cgd of both transistors). Also, they depend on the capacitance you are driving. Spikes are large, for instance, if you are driving small capacitance with large inverter. If you want to...
Yes, it is weird. I am worried because my next chip will mostly work in subtreshold and it is similar technology, UMC 180nm. Obviously, you have to be very careful with the models and during MC/corner simulations. Please post here if you discover what was the problem.
I have read your paper, nice work btw. However, I think that resistors are probably the source of your problem. I dont see anywhere in you paper discussion on resistor process variations, This well resistor you used in osc have huge process variation (as 30%), you also use resistors to generate...
The chart that you have attached presents efficiency dependance on output current while all other variables you have mentioned are fixed (nominal values).
1. If you just connect the supercap on the output it is equivalent to not having a load at all, I_out will depend on many things and it...
If you focus on the center ring only, you can see two identical "transistors" without diff layer on both sides. Those are so called dummy transistors and they are used for matching purposes only (two in the middle are probably differencial pair). During fabrication outer layers are...
Thank you for your answer. Number 3 gives the same result, since Tox=4nm. I will also leave some margin (at least 1Vth).
Vin is 0.1 to 0.5V and Vout 1.8V, it is for energy harvesting applications.
Hi,
I am designing a low power boost converter in 180nm CMOS. I am a beginner in the field, so any advice is welcome. I would like to drive my switches with maximum possible gate voltages in order to minimize their Ron (maximize efficiency) and to be safe at the same time. So, I am wondering...
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