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Recent content by jj00510

  1. J

    question on power analysis, after synthesize the verilog RTL model

    Thank you for your response. So, even if the result differs from expectations, can I consider it a reliable outcome as long as it satisfies the timing condition? I have no idea whether the result came from my misconfigured constraints or if it's just an optimized outcome. Thank you
  2. J

    question on power analysis, after synthesize the verilog RTL model

    Is it possible that the reult of power analysis of disign improved after adding more function in verilog code?
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