Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi adunsmoor,
I am new to OCv and AOCV concept. From the articles which you pointed, I came to know that OCV is optimistic for shorter paths. How can OCV be optimistic for shorter paths?
As per my understanding in OCV a common derate value is applied to all the clock and data paths. Since we are...
Hi All,
I am doing DFT insertion for the first time. Now I am stuck fix a violation " Reset being used as D input to a DFF".
I tried to fix it using autofix option by enabling -fix_data enable.
But during preview_dft it is saying that no violation needs to be autofixed.
Can anyone help me to...
hi all....
i am interfacing an lcd with fpga. i want to convert the character to ascii so that i can display it using an lcd. i am storing the characters to be displayed in a string and using for loop i am retrieving it one by one. but i need to convert it to ascii. i am using vhdl. is there any...
hi....
the problem is solved. it was a problem with my code. i replaced the loop statements with if construct. then it worked. the problem was whenever positive clock edge comes the program terminates. also i learned that you can change the time for which waveform is displayed by right clicking...
i ran behavioral simulation by selecting the test bench. mask is declared as inout as i am reading as well as writing value to it. first i assigned value to mask within the second process but error was displayed when i synthesized it saying "its a bad assignment". thatsy i wrote its value in...
hi sir,
it was the problem with my code. was not entering the loop. So i modified the code but it doesnt produced any delay. i think the problem is that the signal mask is always having a value 'U'. can you pls help me in finding the error. i tried alot but it was not fruitful. the code which i...
hi....
for simulating my project i created a test bench using ise 14.3 .. but when the behavioral model is run only waveforms upto 500ps are displayed. the clk period is 1ns. how can i increase the time for which waveform is displayed?
Dear barry,
in the first case i set up a counter , ie; i incremented it frm 0 to 1000000 and outside the loop i am reseting the variable to 0 so that it will do the same when it enters the loop next time. That is what I meant while writing the code. Incrementing a counter as well as decrementing...
as it is not possible to produce synthesizable delay using "wait for " statement i wrote the following code. But it shows some error , I did'nt understand what the error was. i wrote the following code within the process statement.
process(clk)
variable count:integer;
begin
.
.
.
.
.
.
L1:loop...
hi.....
I am also new to the world of FPGA... I need to interface an lcd module with fpga. My doubt is that whether i need to provide the ASCII value of each character to be printed separately or can i define an array of the characters to be printed and given to the data bus of LCD one by one...
Thanks for replying.......
so if I do some mathematical manipulations for eg if i multiplied the timer's value by 5 (tmro*5,after disabling the clk to counter) and i compared the result with its hex equivalent, wil i get the same result as if i compared with the decimal equivalent???? as per...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
