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Recent content by jing10273

  1. J

    What is the relationship between ESD and latch up?

    plz make your question more clear.what do you mean? in my opinion,there is no tight relation between the ESD and latch up. ESD is to protect the core;Latch-up is because of the parasitic effect of the transistors.
  2. J

    The difference in use of dummy transistor and dummy pole

    Re: Dummy Transistor The dummy transisitor is used for the purpose of transistor matching and guarding,especially in differential amplifier,it include not only the dummy poly,but also the dummy diffusion. the dummy poly is used for the purpose of lithography in the process,to ease the problem...
  3. J

    IC Designer Wanted (Singapore) 10 Permanent vacancies

    some infomation about the company,job types,salay and etc.???????
  4. J

    Dose Analog IC Design & Layout have a good future?

    My opinion is that analog will change but it still has a good future.For our students and engineers,we must prepare for these changs such as quatum and molecular electronics.
  5. J

    How to design ADC converter and how it recognizes incoming signals?

    Re: adc converter design You'd better study some classes and reading several books and papers on AD/DA design.youmay find these in download session in this forum.
  6. J

    Please help me with designing transceiver 2.4 Ghz

    Re: trnasceiver 2.4 Ghz What's the application field this transceiver used in?
  7. J

    does anybody have EE315 coursenote of B.Wooley of stanford ?

    b. wooley ee315 EE314 os in a winter season course,you may find the course notes and exercise on the stanford class site in Feb and Mar.
  8. J

    How does psub2 layer affect the mask preparation and separate the substrates?

    psub2 layer yes ,it is a virtual layer only exsited in EDA tools to satify aome rules and for the purpose of convinience,used for LVS,etc.In maufacturing , it does't exist,so you can't use it for any real application.
  9. J

    Does Layout engineers complete DFM and release the GDS?

    Re: DFM In lithography ,the illumination source wave length is 193nm ,but the feture size is 90nm,65nm or 45nm,the phsycical dicrimination limite is 1/2 wavelength,so diffration,and intrference occure,the transfered pattern may be distorted even vanished on the wafer when projecting,so...
  10. J

    Detailed description of the Deep N well

    Re: Deep N well not only for isolation,but also for noise rejecting and latch-up effect
  11. J

    Can you explain this?

    you.d better consult some semiconductor device structure and physics books.

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