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Recent content by jinbow

  1. J

    VHDL - Register from Procedure ??

    Hi All, Thanks for all the comments and information. FYI. Both devices/tools, listed below, did properly infer that Procedure as a Register without a Process (called directly under Architecture). Microsemi (Actel) - ProAsic3 using Libero Xilinx - Kintex using Vivado Thanks, ALbert
  2. J

    VHDL - Register from Procedure ??

    Hi All, Is it ok to have a Register made out of a Procedure (sub program) in VHDL?? Is it synthesizable?? EXAMPLE: procedure REG (signal clk : in std_logic; signal d : in std_logic; signal q : out std_logic) is begin if rising_edge(clk) then q <= d; end if...
  3. J

    VHDL question - full adder using variable vs signal in Process

    Thanks TD, great explanation!! What is LRM by the way???
  4. J

    VHDL question - full adder using variable vs signal in Process

    Hi all, I'm trying to do a 8-bit full adder example in Pedroni's VHDL book. Below is his code which works when simulated: ================================================= library IEEE; use IEEE.std_logic_1164.all; entity temp is generic( bits: positive := 8); port ( cin : in std_logic...
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