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yes, it is a labsheet given by my lecturer and since i am out of idea despite many attempts, here i am, seeking help. isn't it what this forum's all about? to discuss and share? fyi i came up with the coding myself with of course some assistance with from friends. therefore, i really do not...
hi, i need help with my vhdl code:
entity DU is
Port ( gcd_inA, gcd_inB : in STD_LOGIC_VECTOR (3 downto 0);
selP0 : in STD_LOGIC;
selQ0 : in STD_LOGIC;
ldP : in STD_LOGIC;
ldQ : in STD_LOGIC;
ldG : in STD_LOGIC;
reset ...
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