Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by jery_cn

  1. J

    Is it possible to reconvert the scan flip flop to normal flip flop?

    Re: replace scan flop with ord. flop how can we convert scan-clock gating latch back to normal clock gating latch?
  2. J

    How to fix this clock gating check problem?

    How can this "mux" avoid glitch on mux's output which is a clock?
  3. J

    How to fix this clock gating check problem?

    Thanks for your information! what is the "using a 2 input mux",Does this can resolve the dynamic gating signal?
  4. J

    How to fix this clock gating check problem?

    Lastly ,I encount clock check problem.Description as follow : RTL : always @(posedge clk0) clk_gate <= .... or or(.Y(clk_gate_out),.A(clk0),.B(clk_gate)); always @(posedge clk_gate_out) ..... ..... DC: create_clock .... clk0 set_clock_gating_check...
  5. J

    Hold time violation in DFT insertion

    DFT Compiler I think you should set don't douch attribute on TE and TI signals. thanks.
  6. J

    discrete fourier transform basics

    synopsys dft compiler tutorial I think the DFT COMPILER PAPAERS IS ENOUGH.
  7. J

    does this circuit have problem in DFT? how to solve??

    Is this can cause 3-state conflict? and using dft compiler can solve this problem by some relative commands. Maybe set_scan_configuration -external_tristates enable_one .. GoodLuck.
  8. J

    How to know how many scan chains do I need for a chip (DFT)?

    DFT question by default,a scan chain to one clock .but you can identify the total scan-chain you need by mix multi clock and their edge. there is some configuture command and option in doing this. find them in dft compiler manual.Good Luck.
  9. J

    Nanosim read netlist problems.

    nanosim -n netlist_name ... Do this way can not pass?
  10. J

    Advanced Synopsys DC workshop

    Synopsys DC how can i get this book with my only 0.5 point here?so funny with this situations. and if I want to download this book,the only way is to do something usful to others people? if so,aha. who can get my help if I am a new guy in this field?can anybody tell me?
  11. J

    Synopsys DC chip synthesis workshop!

    synopsys workshop sorry.I am searching a book name <advanced.asic.chip.synthesis>. and donot know if this one edacw1 privided is it. and when I search it in google.I found this book exist in this forum. so everyone help's is thanks.
See more

Part and Inventory Search

Back
Top