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Hi, thanks for your reply.
Images are correct I think. As Ø1 close, the reservoir capacitor CR is charged from VDD, while the input & output of the amplifier are both reset to VCM. In this moment, sources of input cmos transistors are disconnected to supply.
While during the amplification...
Hi all! Recently I am studying the dynamic amplifier, floating inverter amplifier (FIA). It confuses me that how can we simulate the open loop gain and phase margin that given from papers. As for FIA circuit, its operating points and supply voltage various with time during the amplification...
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