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A 8-bit address with 4-bit width LUT and 4 level pipeline will be ok for you.
Or a 16-bit address with 5-bit width LUT and 2 level pipeline?
Hope this helps
Help in VHDL
elsif (Clock'event and Clock = '1') then
if(Channel_A'event and Channel_A = '1') then
Q II can't refer any register from these two lines and i think you can not expect Q II understand it while no register can meet your requirement :)
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