Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all.
I'm simulating 0.2um FD SOI MOSFET using silvaco.
i found if I reduce buried oxide thickness, threshold voltage decrease.
I just mean threshold voltage (not amount of threshold voltage reduction compared with long channel device)
But I don't know the exact dependence between threshold...
i mean, Is there any conventional ratio between channel length and parameters like oxide thickness,junction depth and substrate doping?
if so, why?
I want to simulate 0.3um NMOS using silvaco. but i don't know how to determine oxide thickness, junction depth and substrate doping.
please help.
How mos parameters(oxide thickness, junction depth, Nsub) affect to Vt,SS, Ioff and DIBL respectively?
For example, if oxide thickness is reduced, Vt, SS will decrease. i'm not sure about cases of Ioff and DIBL.
i want to know all those relations between them.
if oxide thickness is...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.