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I will think about the reply by j_andr. Will try to work on it and see if this is wghat can be done.
ABout the functions, I can convert the components to functions but as I mentioned earlier my components are rather big programs with divider, adder components in it. So I am not sure if I can...
Thanks for your reply. It makes sense. I guess the next question would be the components are to be used in every loop till the condition is met and everytime the inputs to the components are updated from the previous loop, how do I update the inputs.
According to my knowledge your suggestion...
well I understand that components cannot be instantiated in a process. I don't know if I can explain it better.
The algorithm I am trying to implement uses a while loop and within that loop uses a couple of components mostly division related. While coding with VHDL, I cannot use WHILE loop so...
When I try to map components within a process, all the components are ignored and not recognized.
Is there some way to use components within a process?
arithmetic shift
Thanks it woked like a charm. I was using a signed divder to perform divide by 4 as I could not get the arithmetic shift right to work Thanks a bunch!!!
arithmetic shift
USE IEEE.NUMERIC_STD.ALL;
this is the library I am using.
Added after 4 minutes:
I changed the command from
pp0 <= std_logic_vector(unsigned(p0) srl 2); to using
pp0 <= std_logic_vector(signed(p0) srl 2); it does not work. It compiles fine but still shifts right and adds...
Hi,
pp0 <= std_logic_vector(unsigned(p0) srl 2);
This is what I used to shift left logically and it works perfectly. When I try to do "sra" instead of "srl" I get error. I realized my program deals with negative integers as well so I will have to perform arithmetic shift. Can someone help me...
Hi,
can someone guide me to a good book or link for understanding divider algorithm. I am interested pipelined dividers or any fast dividers and was wondering where I can find good books or links.
I am reading Parhami - Computer Arithmetic and it seems to be good but more information I have the...
Divider
Hi,
Does anyone know the algorithm used for the divider posted on OpenCores.
https://www.opencores.org/cvsweb.shtml/dividers/rtl/verilog/div_uu.v
I am more familiar with VHDL, and it's a little bit difficult for me to understand the divider code in verilog so was wondering if anyone...
Hi,
Is there any problem with using while loop at the start of the program in VHDL and Xilinx ISE. I keep getting parse error. The algorithm that I have will work best with While Loop and so I was wondering if anyone can point out anything with regards to while loop. Here's few lines frm my...
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