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Recent content by jeffsky520

  1. J

    Please help provide some clues to fix pipeline adc's bug

    Hi,all, Pipeline ADC test shows wrong output as attached pictures. From that we can see ADC output data jumps in one direction only with medium amplitude signals' injection that puzzles me greatly. so can anyone please help provide some clues to fix this bug? Any suggestion and advice will be...
  2. J

    problem with the output of ADC when sampling rate is high

    What about your comparator?
  3. J

    a urgent question about pipelined adc

    hi, I can not agree with your viewpoint . I think Even if you use charge-redistribution S/H structure, cap mismatch only brings gain variation but not affect S/H performance obviously if all device can work well in saturation. Added after 3 minutes: Hi, if S&H has gain > 1 ==> 1LSB...
  4. J

    CMFB for high linearity and low noise design

    1, it only need one CMFB ckt here; 2, resistors add little noise because of opamp gain.
  5. J

    about pipelined adc,ergent

    hi please describe in detail your question, anyway, I think, the problem maybe exists at OP AMP capacitance driving and timing .
  6. J

    What is the salary range for embedded engineers (3.9 years) in Singapore?

    salary in singapore Then how is Analog circuit designer?
  7. J

    op-amp design problem

    polarity connection is right? confused. Could you please explain it clearly ? Thanks.
  8. J

    What is meant by rail to rail opamps?

    rail to rail opamps Also input stage and cascode stage can be merged (such as folded cascode with complementary input pairs). Generally output stage reaches rails relatively.
  9. J

    about bandgap TC curve being concave instead of protruding

    about bandgap TC curve I have also met the same situation, but have no idea about that even now.
  10. J

    hspice no convergence

    **error** no convergence in operating point check your circuit first to be sure correct connections.
  11. J

    How to determine the capacitances of the 2 metal

    Refer to process manual for parasitic capacitance between metals.
  12. J

    HSPICE error message please help.

    I met the same question and didn't know the reason. Maybe it's not related to simulation time, because my transit time is just 5us with 1ns time step.
  13. J

    Bias circuit for OTA needed

    it's difficult to achieve large bias current through this structure , I think, because of limited delta(vgs) and resistance.
  14. J

    question about gm/ID=2/(Vgs-Vt)?

    deeply understanding. Thanks.
  15. J

    ask for help about cascading of pipelined adc

    you'd better make your question clear first, show timing figure or someting else.
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