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vdsat definition
May be it's an old question, but i think it's important. As we know, BSIM3 spice model does not give a clear definition for 'vdsat', and vdsat is always not equal vgs-vth.
And so, which can be taken as 'criterion' in out circuit design.
But since the gain varies with frequency, divide output noise by DC gain?And we know that beyond the unit gain point, gain becomes negative, at this time stlii divide output noise by gain, the input noise is ampilfied ,and is unreasonable.
I want to design a comparator, the equivalent input noise of it must be less than 1/2 LSB of the syestem.But how can I measure the equivalent input noise exactly?
Use the nosie summary of cadence, i can get a precise total output noise ,which will be constant when the stop frequency near...
Many people try hard to enhance tbe PSRR of eh bias circuit, but they all focus on the PSRR+ that is VDD. But much of BGR take the GND as refrence , if the circuit is in a bad surroundings, such as large GND noise ,the PSRR- is also inportant. Do
we really need both PSRR+ and PSRR- in bias...
I want to use this configure to test the SC ampifier's settle time.VIC is common mode dc input.VID is a step signal .The 10 gig resistor is to replace the MOS swith to set the OTA's dc point.
the above test is right or wrong ??
Thanks!!
when i test OTA's settle time use Hsipce ,what kind of step siganl can be added ?
ideal one?(has zero raise time)or with small raise time?
if OTA settle with 10ns,what the raise time should be?
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