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You will have some muxing logic at top level which will control the clocks. You can have multiple clocks enter through same port, physically there will be only one clock at a time. So there will be a physically exclusive relation defined between clk1 and clk2 if you check the constraints
Why do I need multi stage clock gating? I can insert a root ICG at clock source and that should cut off my clock. What is the need to have downstream clock gates ?
I wanted to understand if IR drop can be fixed with VT swaps. Swap faster switching cells (LVT/ULVT) to RVT should help with IR drop? How does downsizing help with IR drop? Is it because of internal resistance reduction ?
SPEF file has R and C values which the STA tool uses to calculate and arrive at cell and net delays and compute the crosstalk information.
SDF has annotated delays and cells are annotated with the delays. STA tool just has to annotate these delays and there is no computation involved.
Usually...
Both are reporting options and use different path tracing algorithms.
GBA: This is fast, slightly pessimistic and uses worst values across each cell in the path.
PBA: More accurate, time consuming and uses exact path tracing and exact propagation values.
GBA is used for most of the design...
Assuming you are speaking of PBA, this option is for reporting. Usually the reports are generated on graph based analysis and the numbers are pessimistic as the worst case transitions/delays are assumed.
In path based analysis, you trace the actual path and transitions resulting is accurate...
As mentioned, during block closure, you have budgeted values for the clock. While instantiated in the top, the clock arrival might be different from that you have specified and hence the violation.
Other thing is if wires are running over your block, they can have crosstalk effects due to...
The max transition limit if specified over the lib limit, will be usually lesser than the lib limit. Even if the limit set is higher, the STA tools will pick up the worst case and perform the analysis.
Buffer has higher delay inherently as it is nothing but back to back inverters by design. You can go with the buffer-inverter flow, but please make sure that the clock phases are as per requirement.
Regards
Jeevan
It will take the first one and ignore all other files. I would suggest you to run parallel runs to go ahead with your experiment. You can also use "remove_annotated_parasitcs" to remove the parasitics
Regards
Jeevan
You can use both, not an issue unless you end up in inverting the clock phase. Using inverters helps in reducing the area requirement, hence preferred in congested designs.
Regards
Jeevan
VDD being a always high net can inturn affect the shielded net if there are glitches in power supply. So the shielding is preferred in VSS to couple the caps to ground.
set_operating_condition -analysis_type on_chip_variation to set the analysis to OCV.
Now you can set the derates by set_timing_derate -early -cell_delay -net_delay <derate value> for min derating
set_timing_derate -early -cell_delay -net_delay...
Wireload and interconnect are modelled in pre layout stage and .libs are used to compute the timing. Post layout the actual RC values are taken into account for accurate analysis.
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