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I thought the OP wanted a 32-bit counter. His original code was using a 32-bit integer but limiting its range to 0 through 255. Perhaps I mistook the OP's intentions?
Regards,
jdb2
I didn't say they aren't synthezisable; I said they "might" not be synthesizeable. I've never had many occasions to use Verilog integers for synthesis -- I use them mainly for eg. for loop variables to generate code. I thought I remember having problems with Verilog integers with regard to...
There are several problems with your code. First, you're using the integer type, which isn't always synthesizable -- you should use a reg type or logic type ( as it appears you code is SystemVerilog from the implicit continuous assignment ) for the counter variable ( Also, the "integer" data...
The first problem with your code is that you're using the reserved keyword "genvar" for the module name -- you'll have to use a different name. The second problem is the lack of a name for the for loop block in the generate statement. Furthermore the expression "xor g1(z1(i),x(i),y(i));" is a...
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