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Hi, gnomix!!!!!!!!!!!11
Tks very very very very very.....................MUCH to you!
It can works now!
tks you!!!!!!!!!!!!!!!!!!!!!!!!!!1^^
but what flow do you follow to do the test_compiler????
jazz
HI, gnomix:
Tks very much for your suggestion, I will try it!
Appreciate very much1 ^^
BTW, what the complex flow you folow for the test_compiler?
jazz
and I have the atpg cobflicts show that........
report_test -atpg_conflicts
Warning: Design 'test' has '4' unresolved references. For more detailed information, use the "link" command. (UID-341)
****************************************
Report : test
-atpg_conflicts
Design : test...
and the reference manual of DC says that, the bidirectional cell or tristate may cause the low fault coverage or may be fail to gen the test patterns........
jazz
Hi, gnomix , tks for your reply, ......
ya, there are some design rule viloation" in my design, but the scan _chanin is insert successful for the syncronous clock, and when I replace the bidirection port cell to the output cell, the tools can gen the test_pattern successfuly, .........so, i...
Any one can help me!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!i appreciate very much!!!!!!!!!!!
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when I run the DC to gen the test pattern in my design, tools shows the fault coverage is zero..........following is my cmd and message...
1. )...
OK, but, how about the level of the spice model? level_1~ level_3? Generally, the most accuracy of models for individule Fab are level_49 or above ( considering the VLSI design). Does anyone know what is the level support for EDALIB?
jazz
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