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Tried defining vertual clocks and assigning 0 input and output delays wrt the appropriate sigs. It seems the tool only looks at one clock and optimises for it. In this case vclockSlow. See constraints below:
Constraints:
#
# Clocks
#
define_clock -name {clk40} -period 25.000...
define_input_delay
So say I have a bunch of combinitorial paths:
Path A has a 7ns m@x delay
Path B has a 5ns m@x delay
Path C has a 3ns m@x delay
specifying this in synopsys is easy using the set_max_delay option.
Without over constraining paths A and B. What is the simplest way to...
synthesis define_input_delay
Are there any scripts out there to convert between synopsys constraint scripts and synplicity constraint scripts?
Also, it seems there is not a direct way to specify combinational delays (ie set_max_delay) in synplicity. Is this true? Must I use a referece to a...
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