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Recent content by jayavelbalu

  1. J

    what is the advantage of PT's timing analyasis ability?

    1.As previously mentioned, the block level static timing analysis is done using DC. 2.The chip-level static timing can be performed using the STA (Primetime). 3.Primetime is the Synopsys stand-alone sign-off quality static timing analysis tool that is capable of performing extremely fast static...
  2. J

    Advice on floor planning a SOC chip

    Re: floor plan flooplan is done before the placement in ASIC flow there is pdf down for ur reference

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