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perl hierarchy browser
Hi ,
Have any one used Perl TK to generate a Hierarchy Browser . I am trying to do one .
If you have some info can u pls share it with me ..
-Jay
xilinx comparator delta sigma
me too doin the project in sigma delta ADC design.
let me say what steps i followed to bring out the chip
First i took the required spec ,
mine was 0.35u CMOS 70Mhz continous time bandpass ADC .
There is basically a filter which is the major part of the design...
Can anyone tell the best architectures for the basic elements like adder ,
accumulator, multiplier.
i found that wallace tree multiplier is the best multiplier architecture
anyone can comment on it
set_clock_transition
can anyone tell me how to select set up time, hold time , rise time , fall time.
is it depend on the frequency of the design or the technology library
do we need to give transition time for the output pins also
advance thanks
waiting for reply
LOW POWER ASIC
Does anyone working on low power,
If yes which is the best way to reduce power
is by doing architectural analysis or gate level analysis
Sample ASIC Design flow
can anyone tell me good website which provide me sample netlist to asic design flow, so that i can do only P & R, is there any sample verification modules , which talks abt verification plan , test plan , test cases
waiting for good reply
ASIC with MAGMA
does anyone tell how far this tool is better than other tools like cadence any synopsys.
can anyone tell wht is best feature in magma
and why it is advantageous than others
how far it cope up with low power vlsi
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