Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
sir,
i have trying to find the delay of a circuit using the formula from ivan sutherland d=(gh+p)T.
the reason is ,i am designing a surfing circuit for high speed interconnects. i want to verify mathematically that my circuit works at this speed.
so, to implement the formula i need the values...
sir,
i encountered error when i transported the gds from cadence to synopsys and while doing DRC checking.
the error said it was related to HR to HR min distance
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.