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Recent content by jason_class

  1. J

    output residence of transistor

    Dear Fan I think you are absolutely correct! That is the only possible reason to explain the low Ron Thank you for spending time in this simple question with effort! Xie xie best rgds Jason
  2. J

    output residence of transistor

    Dear All Actually Ron and Rsd is the same isn't it? Usually I notice that the Ron of mosfet is very high kohm or Mohm range. But I do see some cmos pass transistor logic with Ron of just 5 ohm or slightly higher. ANyone know if this 5ohm refers to the Ron of mosfer aor Rsd? Or it is simply...
  3. J

    Need info about latch up failure

    Re: Latch up Dear Seng Yee & All Thanks a lot everyone. Your advice are very useful. I am quite agree with what Seng Yee mentioned here and that leads me to some books to understand better. I indeed find some relation between ESD and IO device. Currently still reading for better digestion...
  4. J

    Need info about latch up failure

    Re: Latch up Dear All To All who have commented and given the document, I really appreciate your help! Let me digest the material and shall be back for further discussion. By the way, if anyone has any experience in process induced latch up , kindly share with me your opinion. Thank you All...
  5. J

    Need info about latch up failure

    Dear All I need some help to understand more about latch up failure. Usually, latch up failure happens are due to improper layout of design OR due to process issue? I heard that often latch up failure happens in IO mos. What are they for? Why it is often the case latch up happens at IO mos? Is...
  6. J

    body source voltage of pmos

    Thank you Rich. It is good to see your helpful comment.
  7. J

    What exactly is Technologist from IC design doing?

    Re: Technologist Hi Syukri Thanks for answering about" Technologist" Can I know wher can we get useful knowledge about measuring parameter for different device structure or different process? Any book or website you can recommend? Thank you best regards Jason
  8. J

    body source voltage of pmos

    Hello Everyone I would like to check with you all if SMALL SIGNAL Vbs for pmos is always zero is the bulk and source is at Vdd? Kindly enlighten Thank you all best regards Jason
  9. J

    What exactly is Technologist from IC design doing?

    Technologist Hello All Anyone has the idea what actually a Technologist from IC design does for the job? I know it is something like assisting and giving ic designer advice on the part of process technology influence on circuit design. How to learn such a knowledge? Any site or book teach...
  10. J

    about protecting the copyright of a freelance design

    Hello All I have a question directed by a friend who works as a freelance electronic(chip level, not ic level) designer. He is not into ic design but recently he tried a circuit design in some spice simulator and found it to be working well. He would like to propose the design to company that...
  11. J

    lookin 4 a Analog IC Designer job in Malaysia...

    check website at www.jobstreet.com.my Ok?
  12. J

    new graduate, wanna find a job on RFIC, I'm in CHina.

    what kind of job u want about in malaysia?
  13. J

    Why SOI technology is preffered for RFIC design?

    Re: SOI for RFIC Yes Srini WIll check it out when there are copies in library :) Thanks Jason
  14. J

    Will SOI be acceptable by market in next 5-10 years?

    Thank you so much Scottieman and Humungus Now I got to know why SDE is preffered after Ldd. That's cool. Thank you Scottieman for the enlightening words. Yes Humugus , I saw from somewhere which I forgot(most probably the VLSi book by Prof Stanley Wolf) mentioning the implant ideal profile is...
  15. J

    Will SOI be acceptable by market in next 5-10 years?

    Hello Sky High, Scottieman and Humungus Thank you so much for writing back with so many opinions to share. I know from book that PD SOI's Vth is independent of back gate bias due to its large neutral region in the silicon active film. However FD SOI will have large vaiation in its Vth due to...

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